This invention relates to integrated circuit devices with mixed signal components, e.g. analog and digital sections in the same IC substrate.
Isolation of electrical signals in IC devices has been addressed in the prior art, and a variety of approaches have been developed. Complete isolation has been achieved in power ICs with dielectrically isolated structures. This approach is effective, but costly, and it consumes significant chip area. Junction isolation, i.e. guard rings, is the technique of choice in densely packed VLSI devices. Junction isolation is effective in blocking stray signals that propagate in the vicinity of the surface of the device. However, in ICs that are formed in epitaxial material, where the epitaxial layer is grown on a low resistivity substrate, an additional stray signal path extends vertically through the epi layer and into the low resistivity substrate. Once the signal reaches the substrate it can stray unimpeded to any region of the chip. A proposal for dealing with interference in the substrate is to increase the resistivity of the substrate. Silicon on sapphire (SOS) and similar technologies have been developed which provide a high degree of isolation, but these types of wafers are more difficult to process and are not economical for many applications.
Another approach to IC isolation that was explored in the early 1980s was the use of trenches between circuit components. V-groove trenches were found to consume excessive chip area. The advent of effective anisotropic plasma etching techniques, with which narrow trenches a few microns deep could be routinely formed, was also proposed for isolation. Techniques involving trenches of either kind required backfilling to allow further planar processing, and were, overall, complex and expensive.
Some of these approaches have been combined in principle to produce an isolation technique called triple well isolation. This approach uses a blanket subsurface implant which extends beneath multiple wells. Triple well isolation has been found to be efficient and cost effective. See xe2x80x9cSimulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuitsxe2x80x9d by Nishath K. Verghese, Timothy J. Schmerbeck and David J. Allstot, Second Edition, Kluwer Acedemic Publishers, 1995.
Recent advances in IC design and fabrication make possible the integration of analog and digital circuits on the same IC chip. However, the analog signals are susceptible to interference and the presence of digital signals, or high level analog signals which swing the full voltage range, in the vicinity of analog components allows the digital interference to couple directly into the analog sections of the IC chip. The use of triple well isolation in these ICs is ineffective since the isolation implant, which is typically tied to the voltage of the digital wells, i.e. the digital VDD, actually couples directly the digital voltage swings into the analog wells.
Use of triple well regions within analog circuitry can be problematic even if the triple well region is tied to analog VDD because analog circuits usually contain isolated N regions containing p-channel devices that are meant to be tubbed to some node other than VDD. Since all of the NTUB regions within a triple well region get connected together through the buried layer, existing analog circuitry would have to be redesigned to make it compatible with triple well. Thus, one advantage of the inventive scheme is that analog circuitry that was designed for an analog-only chip with no isolation scheme can be placed onto a mixed analog/digital chip without being redesigned.
We propose an isolation technique for analog/digital subcircuits in a single chip implementation which uses a relatively simple modification of the triple well isolation technique. Having recognized that in triple well isolated circuits using both digital and analog sections the triple well implant channels noise throughout the chip, the triple well deep implant in our modified isolation technique is selectively made just beneath the wells containing digital circuits. Thus only the portions of the chip that operate at digital VDD are isolated with the triple well implant.